CMOS Implementation of a Trained Threshold Logical Element. Part II. Simulation Results and Implementability
Keywords:
Artificial Neuron, Synapse, Trained Threshold Logical Element, Training Algorithm, Step of Trainee, CMOS Technology, Threshold Logical FunctionAbstract
Purpose: Showing the possibility of modern CMOS implementation of an analog-digital logical threshold element which can be trained
to complex logical threshold functions, and finding the limits of its implementability. Methods: SPICE simulation of training the threshold element to complex threshold logical functions and of supporting its analog memory elements in the trained state. Results: It is shown that for threshold element training experiments, the most suitable threshold functions are those which can be represented like Horner scheme, as with their high complexity they have the shortest checking sequences. A threshold element manufactured in CMOS 0.18 micron technology can be trained to an arbitrary threshold function with a threshold not exceeding 144. All threshold logical functions of 11 variables satisfy this restriction, and many functions of a larger number of variables. Practical relevance: The designed trained threshold element has considerably extended functional possibilities. It can be used in logical pattern recognition systems and in new generations of neurochips.